module sccpudataflow (
    input clk,RST,
    input [15:0] Inst,
    input [15:0] memdataout,
    output wire [15:0] PC,
    output wire [15:0] memdatain,
    output wire [15:0] alu_out,
    // output wire [15:0] memADDR,
    output wire wmem,rmem
);

    // wire [15:0] Inst;
    wire [4:0] OP = Inst[15:11];
    wire [2:0] D1 = Inst[10:8];
    wire [2:0] D2 = Inst[7:5];
    wire [2:0] D3 = Inst[4:2];
    wire [7:0] imme1 = Inst[7:0];
    wire [4:0] imme2 = Inst[4:0];
    wire [15:0] Eimme1;
    wire [15:0] Eimme2;

    wire [1:0] alub,regdata,PCsource;
    wire [3:0] aluc;
    wire [15:0] qa,qb,qc;
    wire sext,jr,wreg; 
    wire [15:0] alua_in,alub_in;
    // wire [15:0] alu_out;

    wire [15:0] d;

    wire [15:0] PCadd1,PCaddI1;
    wire [15:0] PC_next;

    assign PCadd1 = PC + 1'b1;
    assign PCaddI1 = PC + Eimme1;
    // assign memADDR = alu_out;
    assign memdatain = qc;

    PC u_PC(
    	.PC_next (PC_next ),
        .clk     (clk     ),
        .RST     (RST     ),
        .PC      (PC      )
    );
    Control_Unit u_Control_Unit(
    	.OP       (OP       ),
        .z        (z        ),
        .alub     (alub     ),
        .PCsource (PCsource ),
        .regdata  (regdata  ),
        .aluc     (aluc     ),
        .sext     (sext     ),
        .wreg     (wreg     ),
        .jr       (jr       ),
        .wmem     (wmem     ),
        .rmem     (rmem     )
    );
    Regfile u_Regfile(
    	.ra   (D2   ),
        .rb   (D3   ),
        .rc   (D1   ),
        .wn   (D1   ),
        .d    (d    ),
        .RST  (RST  ),
        .wreg (wreg ),
        .clk  (clk  ),
        .qa   (qa   ),
        .qb   (qb   ),
        .qc   (qc   )
    );
    SignExtend u_SignExtend(
    	.sext   (sext   ),
        .imme1  (imme1  ),
        .imme2  (imme2  ),
        .Eimme1 (Eimme1 ),
        .Eimme2 (Eimme2 )
    );
    ALU u_ALU(
    	.a       (alua_in       ),
        .b       (alub_in       ),
        .ALUC    (aluc    ),
        .ALU_out (alu_out ),
        .z       (z       )
    );
    mux4x16 alubin_mux4x16(
    	.a0  (qb  ),
        .a1  (Eimme1  ),
        .a2  (Eimme2  ),
        .a3  (16'h0  ),
        .mux (alub ),
        .q   (alub_in   )
    );
    mux4x16 PCsource_mux4x16(
    	.a0  (PCadd1  ),
        .a1  (PCaddI1  ),
        .a2  (alu_out  ),
        .a3  (16'hx  ),
        .mux (PCsource ),
        .q   (PC_next   )
    );
    mux4x16 regdatasource_mux4x16(
    	.a0  (alu_out  ),
        .a1  (PCadd1  ),
        .a2  (PCaddI1  ),
        .a3  (memdataout  ),
        .mux (regdata ),
        .q   (d   )
    );
    mux2x16 aluain_mux2x16(
    	.a0  (qa  ),
        .a1  (qb  ),
        .mux (jr ),
        .q   (alua_in   )
    );
    
    
    
    
    
endmodule